Over the last few decades, the semiconductor industry has undergone a revolution by scaling of semiconductor devices to fabricate smaller, more highly integrated electronic circuits. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is the metal-oxide-semiconductor field effect transistor (MOSFET). The MOSFET transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOSFET transistor is increased and as manufacturing costs are reduced.
A type of device, commonly referred to as a MOS field-effect-transistor (MOSFET), includes a channel region formed in a silicon film or semiconductor substrate beneath the gate area or electrode and between the source and drain regions. The channel is typically doped with a dopant having a conductivity type opposite to that of the source/drain regions. The gate electrode is generally separated from the substrate by an insulating layer, typically silicon diode or silicon oxynitride. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, drain or channel regions. In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner, an electric field is used to control the current flow through the channel region.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. Performance improvements have been obtained by the use of a salicide process (self-aligned-silicide). This process has become a mainstay in semiconductor processing because the process produces contacts having low-ohmic resistance and the contacts are formed using a self-aligned process.
A salicide process involves depositing a refractory metal across the semiconductor topography. After the refractory metal is deposited and subjected to a high enough temperature, a chemical reaction occurs wherever the refractory metal is in contact with a region of bare silicon or polycrystalline silicon. The refractory metal does not react with materials present on a part processed wafer, such as silicon nitride or silicon dioxide. In this manner, metal silicide may be formed exclusively upon the source/drain regions and the upper surface of a polysilicon gate conductor interposed between the source/drain regions. Silicide formation formed upon a polysilicon gate is generally referred to as a polycide gate, which significantly reduces the resistance of the gate structure, as compared to previously used polysilicon gate structures. Silicide formation on the source/drain regions also significantly reduces the resistance of the contacts to the source/drain regions. Any unreacted metal is removed after formation of the silicide.
When forming the silicide, it is important to prevent the silicide from reacting with the sidewalls of the polysilicon gate electrode, so as to prevent shorting between the source or drain and the gate. This is normally accomplished by a pair of sidewall spacers formed on the sidewalls of the gate electrode. The sidewall spacers are typically made of silicon nitride or silicon dioxide and are left on the wafer after manufacture. The refractory metal that forms the silicide when reacted with silicon does not react with the silicon nitride or silicon dioxide sidewall spacers during the annealing process.
In certain processing schemes, it may be advantageous to remove the conventional sidewall spacers to allow other structural arrangements that increase device performance. For example, removing the sidewall spacers containing silicon dioxide or silicon nitride and forming an interlayer dielectric (ILD) consisting of low k dielectric material will enhance device performance, by reducing the parasitic Miller or overlap capacitance between the gate and source, and between the gate and drain. However, the wet and dry etch processes that are conventionally used to strip silicon dioxide or silicon nitride remove some or all of the silicide. Additionally, a wet process to remove a silicon dioxide spacer would also remove some of the shallow trench isolation (STI) oxide typically employed in the semiconductor arrangements. This undesirable etching of the silicide when removing the silicon dioxide or silicon nitride spacers limits the availability of removing these spacers to enhance device performance.